#!/usr/bin/env python3
# -*- coding: utf-8 -*-

REG_TAB = [
    ('B'   , 'B'   , ''    , 'iota'),
    ('H'   , 'H'   , ''    , 'iota'),
    ('S'   , 'S'   , ''    , 'iota'),
    ('D'   , 'D'   , ''    , 'iota'),
    ('Q'   , 'Q'   , ''    , 'iota'),
    ('V8b' , 'V'   , '8B'  , 'iota'),
    ('V16b', 'V'   , '16B' , 'iota'),
    ('V2h' , 'V'   , '2H'  , 'iota'),
    ('V4h' , 'V'   , '4H'  , 'iota'),
    ('V8h' , 'V'   , '8H'  , 'iota'),
    ('V2s' , 'V'   , '2S'  , 'iota'),
    ('V4s' , 'V'   , '4S'  , 'iota'),
    ('V1d' , 'V'   , '1D'  , 'iota'),
    ('V2d' , 'V'   , '2D'  , 'iota'),
    ('V1q' , 'V'   , '1Q'  , 'iota'),
    ('Vib' , 'Vidx', 'B'   , 'iota << 8'),
    ('Vi4b', 'Vidx', '4B'  , 'iota << 8'),
    ('Vih' , 'Vidx', 'H'   , 'iota << 8'),
    ('Vi2h', 'Vidx', '2H'  , 'iota << 8'),
    ('Vis' , 'Vidx', 'S'   , 'iota << 8'),
    ('Vid' , 'Vidx', 'D'   , 'iota << 8'),
]

SYS_REG_TAB = """
op0	op1	CRn	CRm	op2	Access	Mnemonic	Register
10	000	0000	0000	010	RW	OSDTRRX_EL1	OSDTRRX_EL1
10	000	0000	0010	000	RW	MDCCINT_EL1	MDCCINT_EL1
10	000	0000	0010	010	RW	MDSCR_EL1	MDSCR_EL1
10	000	0000	0011	010	RW	OSDTRTX_EL1	OSDTRTX_EL1
10	000	0000	0100	010	RW	MDSELR_EL1	MDSELR_EL1
10	000	0000	0110	010	RW	OSECCR_EL1	OSECCR_EL1
10	000	0000	m[3:0]	100	RW	DBGBVR<m>_EL1	DBGBVR_EL1
10	000	0000	m[3:0]	100	RW	DBGBVR<m>_EL1	DBGBVR_EL1[]
10	000	0000	m[3:0]	101	RW	DBGBCR<m>_EL1	DBGBCR_EL1
10	000	0000	m[3:0]	101	RW	DBGBCR<m>_EL1	DBGBCR_EL1[]
10	000	0000	m[3:0]	110	RW	DBGWVR<m>_EL1	DBGWVR_EL1
10	000	0000	m[3:0]	110	RW	DBGWVR<m>_EL1	DBGWVR_EL1[]
10	000	0000	m[3:0]	111	RW	DBGWCR<m>_EL1	DBGWCR_EL1
10	000	0000	m[3:0]	111	RW	DBGWCR<m>_EL1	DBGWCR_EL1[]
10	000	0001	0000	000	RO	MDRAR_EL1	MDRAR_EL1
10	000	0001	0000	100	WO	OSLAR_EL1	OSLAR_EL1
10	000	0001	0001	100	RO	OSLSR_EL1	OSLSR_EL1
10	000	0001	0011	100	RW	OSDLR_EL1	OSDLR_EL1
10	000	0001	0100	100	RW	DBGPRCR_EL1	DBGPRCR_EL1
10	000	0111	1000	110	RW	DBGCLAIMSET_EL1	DBGCLAIMSET_EL1
10	000	0111	1001	110	RW	DBGCLAIMCLR_EL1	DBGCLAIMCLR_EL1
10	000	0111	1110	110	RO	DBGAUTHSTATUS_EL1	DBGAUTHSTATUS_EL1
10	000	1001	1101	00:m[0]	RO	SPMCGCR<m>_EL1	SPMCGCR_EL1
10	000	1001	1101	011	RW	SPMACCESSR_EL1	SPMACCESSR_EL1
10	000	1001	1101	011	RW	SPMACCESSR_EL1	SPMACCESSR_EL2
10	000	1001	1101	011	RW	SPMACCESSR_EL1	SPMACCESSR_EL1
10	000	1001	1101	011	RW	SPMACCESSR_EL1	SPMACCESSR_EL2
10	000	1001	1101	100	RO	SPMIIDR_EL1	SPMIIDR_EL1
10	000	1001	1101	101	RO	SPMDEVARCH_EL1	SPMDEVARCH_EL1
10	000	1001	1101	110	RO	SPMDEVAFF_EL1	SPMDEVAFF_EL1
10	000	1001	1101	111	RO	SPMCFGR_EL1	SPMCFGR_EL1
10	000	1001	1110	001	RW	SPMINTENSET_EL1	SPMINTENSET_EL1
10	000	1001	1110	010	RW	SPMINTENCLR_EL1	SPMINTENCLR_EL1
10	000	1110	1011	111	RO	PMCCNTSVR_EL1	PMCCNTSVR_EL1
10	000	1110	10:m[4:3]	m[2:0]	RO	PMEVCNTSVR<m>_EL1	PMEVCNTSVR_EL1[]
10	000	1110	1100	000	RO	PMICNTSVR_EL1	PMICNTSVR_EL1
10	001	0000	0000	001	RW	TRCTRACEIDR	TRCTRACEIDR
10	001	0000	0000	010	RW	TRCVICTLR	TRCVICTLR
10	001	0000	0000	110	RO	TRCIDR8	TRCIDR8
10	001	0000	0000	111	RW	TRCIMSPEC0	TRCIMSPEC0
10	001	0000	0001	000	RW	TRCPRGCTLR	TRCPRGCTLR
10	001	0000	0001	001	RW	TRCQCTLR	TRCQCTLR
10	001	0000	0001	010	RW	TRCVIIECTLR	TRCVIIECTLR
10	001	0000	0001	110	RO	TRCIDR9	TRCIDR9
10	001	0000	0010	001	RW	TRCITEEDCR	TRCITEEDCR
10	001	0000	0010	010	RW	TRCVISSCTLR	TRCVISSCTLR
10	001	0000	0010	110	RO	TRCIDR10	TRCIDR10
10	001	0000	0011	000	RO	TRCSTATR	TRCSTATR
10	001	0000	0011	010	RW	TRCVIPCSSCTLR	TRCVIPCSSCTLR
10	001	0000	0011	110	RO	TRCIDR11	TRCIDR11
10	001	0000	00:m[1:0]	100	RW	TRCSEQEVR<m>	TRCSEQEVR[]
10	001	0000	00:m[1:0]	101	RW	TRCCNTRLDVR<m>	TRCCNTRLDVR[]
10	001	0000	0100	000	RW	TRCCONFIGR	TRCCONFIGR
10	001	0000	0100	110	RO	TRCIDR12	TRCIDR12
10	001	0000	0101	110	RO	TRCIDR13	TRCIDR13
10	001	0000	0110	000	RW	TRCAUXCTLR	TRCAUXCTLR
10	001	0000	0110	100	RW	TRCSEQRSTEVR	TRCSEQRSTEVR
10	001	0000	0111	100	RW	TRCSEQSTR	TRCSEQSTR
10	001	0000	01:m[1:0]	101	RW	TRCCNTCTLR<m>	TRCCNTCTLR[]
10	001	0000	0:m[2:0]	111	RW	TRCIMSPEC<m>	TRCIMSPEC[]
10	001	0000	1000	000	RW	TRCEVENTCTL0R	TRCEVENTCTL0R
10	001	0000	1000	111	RO	TRCIDR0	TRCIDR0
10	001	0000	1001	000	RW	TRCEVENTCTL1R	TRCEVENTCTL1R
10	001	0000	1001	111	RO	TRCIDR1	TRCIDR1
10	001	0000	1010	000	RW	TRCRSR	TRCRSR
10	001	0000	1010	111	RO	TRCIDR2	TRCIDR2
10	001	0000	1011	000	RW	TRCSTALLCTLR	TRCSTALLCTLR
10	001	0000	1011	111	RO	TRCIDR3	TRCIDR3
10	001	0000	10:m[1:0]	100	RW	TRCEXTINSELR<m>	TRCEXTINSELR[]
10	001	0000	10:m[1:0]	101	RW	TRCCNTVR<m>	TRCCNTVR[]
10	001	0000	1100	000	RW	TRCTSCTLR	TRCTSCTLR
10	001	0000	1100	111	RO	TRCIDR4	TRCIDR4
10	001	0000	1101	000	RW	TRCSYNCPR	TRCSYNCPR
10	001	0000	1101	111	RO	TRCIDR5	TRCIDR5
10	001	0000	1110	000	RW	TRCCCCTLR	TRCCCCTLR
10	001	0000	1110	111	RO	TRCIDR6	TRCIDR6
10	001	0000	1111	000	RW	TRCBBCTLR	TRCBBCTLR
10	001	0000	1111	111	RO	TRCIDR7	TRCIDR7
10	001	0001	0001	100	RO	TRCOSLSR	TRCOSLSR
10	001	0001	0:m[2:0]	010	RW	TRCSSCCR<m>	TRCSSCCR[]
10	001	0001	0:m[2:0]	011	RW	TRCSSPCICR<m>	TRCSSPCICR[]
10	001	0001	1:m[2:0]	010	RW	TRCSSCSR<m>	TRCSSCSR[]
10	001	0001	m[3:0]	00:m[4]	RW	TRCRSCTLR<m>	TRCRSCTLR[]
10	001	0010	m[2:0]:0	00:m[3]	RW	TRCACVR<m>	TRCACVR[]
10	001	0010	m[2:0]:0	01:m[3]	RW	TRCACATR<m>	TRCACATR[]
10	001	0011	0000	010	RW	TRCCIDCCTLR0	TRCCIDCCTLR0
10	001	0011	0001	010	RW	TRCCIDCCTLR1	TRCCIDCCTLR1
10	001	0011	0010	010	RW	TRCVMIDCCTLR0	TRCVMIDCCTLR0
10	001	0011	0011	010	RW	TRCVMIDCCTLR1	TRCVMIDCCTLR1
10	001	0011	m[2:0]:0	000	RW	TRCCIDCVR<m>	TRCCIDCVR[]
10	001	0011	m[2:0]:0	001	RW	TRCVMIDCVR<m>	TRCVMIDCVR[]
10	001	0111	0010	111	RO	TRCDEVID	TRCDEVID
10	001	0111	1000	110	RW	TRCCLAIMSET	TRCCLAIMSET
10	001	0111	1001	110	RW	TRCCLAIMCLR	TRCCLAIMCLR
10	001	0111	1110	110	RO	TRCAUTHSTATUS	TRCAUTHSTATUS
10	001	0111	1111	110	RO	TRCDEVARCH	TRCDEVARCH
10	001	1000	m[3:0]	m[4]:00	RO	BRBINF<m>_EL1	BRBINF_EL1[]
10	001	1000	m[3:0]	m[4]:01	RO	BRBSRC<m>_EL1	BRBSRC_EL1[]
10	001	1000	m[3:0]	m[4]:10	RO	BRBTGT<m>_EL1	BRBTGT_EL1[]
10	001	1001	0000	000	RW	BRBCR_EL1	BRBCR_EL1
10	001	1001	0000	000	RW	BRBCR_EL1	BRBCR_EL2
10	001	1001	0000	000	RW	BRBCR_EL1	BRBCR_EL1
10	001	1001	0000	000	RW	BRBCR_EL1	BRBCR_EL2
10	001	1001	0000	001	RW	BRBFCR_EL1	BRBFCR_EL1
10	001	1001	0000	010	RW	BRBTS_EL1	BRBTS_EL1
10	001	1001	0001	000	RW	BRBINFINJ_EL1	BRBINFINJ_EL1
10	001	1001	0001	001	RW	BRBSRCINJ_EL1	BRBSRCINJ_EL1
10	001	1001	0001	010	RW	BRBTGTINJ_EL1	BRBTGTINJ_EL1
10	001	1001	0010	000	RO	BRBIDR0_EL1	BRBIDR0_EL1
10	011	0000	0001	000	RO	MDCCSR_EL0	MDCCSR_EL0
10	011	0000	0100	000	RW	DBGDTR_EL0	DBGDTR_EL0
10	011	0000	0101	000	RO	DBGDTRRX_EL0	DBGDTRRX_EL0
10	011	0000	0101	000	WO	DBGDTRTX_EL0	DBGDTRTX_EL0
10	011	1001	1100	000	RW	SPMCR_EL0	SPMCR_EL0
10	011	1001	1100	001	RW	SPMCNTENSET_EL0	SPMCNTENSET_EL0
10	011	1001	1100	010	RW	SPMCNTENCLR_EL0	SPMCNTENCLR_EL0
10	011	1001	1100	011	RW	SPMOVSCLR_EL0	SPMOVSCLR_EL0
10	011	1001	1100	101	RW	SPMSELR_EL0	SPMSELR_EL0
10	011	1001	1110	011	RW	SPMOVSSET_EL0	SPMOVSSET_EL0
10	011	1110	000:m[3]	m[2:0]	RW	SPMEVCNTR<m>_EL0	SPMEVCNTR_EL0
10	011	1110	001:m[3]	m[2:0]	RW	SPMEVTYPER<m>_EL0	SPMEVTYPER_EL0
10	011	1110	010:m[3]	m[2:0]	RW	SPMEVFILTR<m>_EL0	SPMEVFILTR_EL0
10	011	1110	011:m[3]	m[2:0]	RW	SPMEVFILT2R<m>_EL0	SPMEVFILT2R_EL0
10	100	0000	0111	000	RW	DBGVCR32_EL2	DBGVCR32_EL2
10	100	1001	0000	000	RW	BRBCR_EL2	BRBCR_EL2
10	100	1001	1101	011	RW	SPMACCESSR_EL2	SPMACCESSR_EL2
10	101	1001	0000	000	RW	BRBCR_EL12	BRBCR_EL1
10	101	1001	1101	011	RW	SPMACCESSR_EL12	SPMACCESSR_EL1
10	110	1001	1101	011	RW	SPMACCESSR_EL3	SPMACCESSR_EL3
10	110	1001	1110	111	RW	SPMROOTCR_EL3	SPMROOTCR_EL3
10	111	1001	1110	111	RW	SPMSCR_EL1	SPMSCR_EL1
11	000	0000	0000	000	RO	MIDR_EL1	MIDR_EL1
11	000	0000	0000	000	RO	MIDR_EL1	VPIDR_EL2
11	000	0000	0000	000	RO	MIDR_EL1	MIDR_EL1
11	000	0000	0000	000	RO	MIDR_EL1	VPIDR_EL2
11	000	0000	0000	101	RO	MPIDR_EL1	MPIDR_EL1
11	000	0000	0000	101	RO	MPIDR_EL1	VMPIDR_EL2
11	000	0000	0000	101	RO	MPIDR_EL1	MPIDR_EL1
11	000	0000	0000	101	RO	MPIDR_EL1	VMPIDR_EL2
11	000	0000	0000	110	RO	REVIDR_EL1	REVIDR_EL1
11	000	0000	0001	000	RO	ID_PFR0_EL1	ID_PFR0_EL1
11	000	0000	0001	001	RO	ID_PFR1_EL1	ID_PFR1_EL1
11	000	0000	0001	010	RO	ID_DFR0_EL1	ID_DFR0_EL1
11	000	0000	0001	011	RO	ID_AFR0_EL1	ID_AFR0_EL1
11	000	0000	0001	100	RO	ID_MMFR0_EL1	ID_MMFR0_EL1
11	000	0000	0001	101	RO	ID_MMFR1_EL1	ID_MMFR1_EL1
11	000	0000	0001	110	RO	ID_MMFR2_EL1	ID_MMFR2_EL1
11	000	0000	0001	111	RO	ID_MMFR3_EL1	ID_MMFR3_EL1
11	000	0000	0010	000	RO	ID_ISAR0_EL1	ID_ISAR0_EL1
11	000	0000	0010	001	RO	ID_ISAR1_EL1	ID_ISAR1_EL1
11	000	0000	0010	010	RO	ID_ISAR2_EL1	ID_ISAR2_EL1
11	000	0000	0010	011	RO	ID_ISAR3_EL1	ID_ISAR3_EL1
11	000	0000	0010	100	RO	ID_ISAR4_EL1	ID_ISAR4_EL1
11	000	0000	0010	101	RO	ID_ISAR5_EL1	ID_ISAR5_EL1
11	000	0000	0010	110	RO	ID_MMFR4_EL1	ID_MMFR4_EL1
11	000	0000	0010	111	RO	ID_ISAR6_EL1	ID_ISAR6_EL1
11	000	0000	0011	000	RO	MVFR0_EL1	MVFR0_EL1
11	000	0000	0011	001	RO	MVFR1_EL1	MVFR1_EL1
11	000	0000	0011	010	RO	MVFR2_EL1	MVFR2_EL1
11	000	0000	0011	100	RO	ID_PFR2_EL1	ID_PFR2_EL1
11	000	0000	0011	101	RO	ID_DFR1_EL1	ID_DFR1_EL1
11	000	0000	0011	110	RO	ID_MMFR5_EL1	ID_MMFR5_EL1
11	000	0000	0100	000	RO	ID_AA64PFR0_EL1	ID_AA64PFR0_EL1
11	000	0000	0100	001	RO	ID_AA64PFR1_EL1	ID_AA64PFR1_EL1
11	000	0000	0100	010	RO	ID_AA64PFR2_EL1	ID_AA64PFR2_EL1
11	000	0000	0100	100	RO	ID_AA64ZFR0_EL1	ID_AA64ZFR0_EL1
11	000	0000	0100	101	RO	ID_AA64SMFR0_EL1	ID_AA64SMFR0_EL1
11	000	0000	0101	000	RO	ID_AA64DFR0_EL1	ID_AA64DFR0_EL1
11	000	0000	0101	001	RO	ID_AA64DFR1_EL1	ID_AA64DFR1_EL1
11	000	0000	0101	100	RO	ID_AA64AFR0_EL1	ID_AA64AFR0_EL1
11	000	0000	0101	101	RO	ID_AA64AFR1_EL1	ID_AA64AFR1_EL1
11	000	0000	0110	000	RO	ID_AA64ISAR0_EL1	ID_AA64ISAR0_EL1
11	000	0000	0110	001	RO	ID_AA64ISAR1_EL1	ID_AA64ISAR1_EL1
11	000	0000	0110	010	RO	ID_AA64ISAR2_EL1	ID_AA64ISAR2_EL1
11	000	0000	0111	000	RO	ID_AA64MMFR0_EL1	ID_AA64MMFR0_EL1
11	000	0000	0111	001	RO	ID_AA64MMFR1_EL1	ID_AA64MMFR1_EL1
11	000	0000	0111	010	RO	ID_AA64MMFR2_EL1	ID_AA64MMFR2_EL1
11	000	0000	0111	011	RO	ID_AA64MMFR3_EL1	ID_AA64MMFR3_EL1
11	000	0000	0111	100	RO	ID_AA64MMFR4_EL1	ID_AA64MMFR4_EL1
11	000	0001	0000	000	RW	SCTLR_EL1	SCTLR_EL1
11	000	0001	0000	000	RW	SCTLR_EL1	SCTLR_EL2
11	000	0001	0000	000	RW	SCTLR_EL1	SCTLR_EL1
11	000	0001	0000	000	RW	SCTLR_EL1	SCTLR_EL2
11	000	0001	0000	001	RW	ACTLR_EL1	ACTLR_EL1
11	000	0001	0000	010	RW	CPACR_EL1	CPACR_EL1
11	000	0001	0000	010	RW	CPACR_EL1	CPTR_EL2
11	000	0001	0000	010	RW	CPACR_EL1	CPACR_EL1
11	000	0001	0000	010	RW	CPACR_EL1	CPTR_EL2
11	000	0001	0000	011	RW	SCTLR2_EL1	SCTLR2_EL1
11	000	0001	0000	011	RW	SCTLR2_EL1	SCTLR2_EL2
11	000	0001	0000	011	RW	SCTLR2_EL1	SCTLR2_EL1
11	000	0001	0000	011	RW	SCTLR2_EL1	SCTLR2_EL2
11	000	0001	0000	101	RW	RGSR_EL1	RGSR_EL1
11	000	0001	0000	110	RW	GCR_EL1	GCR_EL1
11	000	0001	0010	000	RW	ZCR_EL1	ZCR_EL1
11	000	0001	0010	000	RW	ZCR_EL1	ZCR_EL2
11	000	0001	0010	000	RW	ZCR_EL1	ZCR_EL1
11	000	0001	0010	000	RW	ZCR_EL1	ZCR_EL2
11	000	0001	0010	001	RW	TRFCR_EL1	TRFCR_EL1
11	000	0001	0010	001	RW	TRFCR_EL1	TRFCR_EL2
11	000	0001	0010	001	RW	TRFCR_EL1	TRFCR_EL1
11	000	0001	0010	001	RW	TRFCR_EL1	TRFCR_EL2
11	000	0001	0010	011	RW	TRCITECR_EL1	TRCITECR_EL1
11	000	0001	0010	011	RW	TRCITECR_EL1	TRCITECR_EL2
11	000	0001	0010	011	RW	TRCITECR_EL1	TRCITECR_EL1
11	000	0001	0010	011	RW	TRCITECR_EL1	TRCITECR_EL2
11	000	0001	0010	100	RW	SMPRI_EL1	SMPRI_EL1
11	000	0001	0010	110	RW	SMCR_EL1	SMCR_EL1
11	000	0001	0010	110	RW	SMCR_EL1	SMCR_EL2
11	000	0001	0010	110	RW	SMCR_EL1	SMCR_EL1
11	000	0001	0010	110	RW	SMCR_EL1	SMCR_EL2
11	000	0010	0000	000	RW	TTBR0_EL1	TTBR0_EL1
11	000	0010	0000	000	RW	TTBR0_EL1	TTBR0_EL2
11	000	0010	0000	000	RW	TTBR0_EL1	TTBR0_EL1
11	000	0010	0000	000	RW	TTBR0_EL1	TTBR0_EL2
11	000	0010	0000	001	RW	TTBR1_EL1	TTBR1_EL1
11	000	0010	0000	001	RW	TTBR1_EL1	TTBR1_EL2
11	000	0010	0000	001	RW	TTBR1_EL1	TTBR1_EL1
11	000	0010	0000	001	RW	TTBR1_EL1	TTBR1_EL2
11	000	0010	0000	010	RW	TCR_EL1	TCR_EL1
11	000	0010	0000	010	RW	TCR_EL1	TCR_EL2
11	000	0010	0000	010	RW	TCR_EL1	TCR_EL1
11	000	0010	0000	010	RW	TCR_EL1	TCR_EL2
11	000	0010	0000	011	RW	TCR2_EL1	TCR2_EL1
11	000	0010	0000	011	RW	TCR2_EL1	TCR2_EL2
11	000	0010	0000	011	RW	TCR2_EL1	TCR2_EL1
11	000	0010	0000	011	RW	TCR2_EL1	TCR2_EL2
11	000	0010	0001	000	RW	APIAKeyLo_EL1	APIAKeyLo_EL1
11	000	0010	0001	001	RW	APIAKeyHi_EL1	APIAKeyHi_EL1
11	000	0010	0001	010	RW	APIBKeyLo_EL1	APIBKeyLo_EL1
11	000	0010	0001	011	RW	APIBKeyHi_EL1	APIBKeyHi_EL1
11	000	0010	0010	000	RW	APDAKeyLo_EL1	APDAKeyLo_EL1
11	000	0010	0010	001	RW	APDAKeyHi_EL1	APDAKeyHi_EL1
11	000	0010	0010	010	RW	APDBKeyLo_EL1	APDBKeyLo_EL1
11	000	0010	0010	011	RW	APDBKeyHi_EL1	APDBKeyHi_EL1
11	000	0010	0011	000	RW	APGAKeyLo_EL1	APGAKeyLo_EL1
11	000	0010	0011	001	RW	APGAKeyHi_EL1	APGAKeyHi_EL1
11	000	0010	0101	000	RW	GCSCR_EL1	GCSCR_EL1
11	000	0010	0101	000	RW	GCSCR_EL1	GCSCR_EL2
11	000	0010	0101	000	RW	GCSCR_EL1	GCSCR_EL1
11	000	0010	0101	000	RW	GCSCR_EL1	GCSCR_EL2
11	000	0010	0101	001	RW	GCSPR_EL1	GCSPR_EL1
11	000	0010	0101	001	RW	GCSPR_EL1	GCSPR_EL2
11	000	0010	0101	001	RW	GCSPR_EL1	GCSPR_EL1
11	000	0010	0101	001	RW	GCSPR_EL1	GCSPR_EL2
11	000	0010	0101	010	RW	GCSCRE0_EL1	GCSCRE0_EL1
11	000	0100	0000	000	RW	SPSR_EL1	SPSR_EL1
11	000	0100	0000	000	RW	SPSR_EL1	SPSR_EL2
11	000	0100	0000	000	RW	SPSR_EL1	SPSR_EL1
11	000	0100	0000	000	RW	SPSR_EL1	SPSR_EL2
11	000	0100	0000	001	RW	ELR_EL1	ELR_EL1
11	000	0100	0000	001	RW	ELR_EL1	ELR_EL2
11	000	0100	0000	001	RW	ELR_EL1	ELR_EL1
11	000	0100	0000	001	RW	ELR_EL1	ELR_EL2
11	000	0100	0001	000	RW	SP_EL0	SP_EL0
11	000	0100	0010	000	-	SPSel	-
11	000	0100	0010	010	-	CurrentEL	-
11	000	0100	0010	011	-	PAN	-
11	000	0100	0010	100	-	UAO	-
11	000	0100	0011	000	-	ALLINT	-
11	000	0100	0011	001	-	PM	-
11	000	0100	0110	000	RW	ICC_PMR_EL1	ICC_PMR_EL1
11	000	0100	0110	000	RW	ICC_PMR_EL1	ICV_PMR_EL1
11	000	0100	0110	000	RW	ICC_PMR_EL1	ICC_PMR_EL1
11	000	0100	0110	000	RW	ICC_PMR_EL1	ICV_PMR_EL1
11	000	0101	0001	000	RW	AFSR0_EL1	AFSR0_EL1
11	000	0101	0001	000	RW	AFSR0_EL1	AFSR0_EL2
11	000	0101	0001	000	RW	AFSR0_EL1	AFSR0_EL1
11	000	0101	0001	000	RW	AFSR0_EL1	AFSR0_EL2
11	000	0101	0001	001	RW	AFSR1_EL1	AFSR1_EL1
11	000	0101	0001	001	RW	AFSR1_EL1	AFSR1_EL2
11	000	0101	0001	001	RW	AFSR1_EL1	AFSR1_EL1
11	000	0101	0001	001	RW	AFSR1_EL1	AFSR1_EL2
11	000	0101	0010	000	RW	ESR_EL1	ESR_EL1
11	000	0101	0010	000	RW	ESR_EL1	ESR_EL2
11	000	0101	0010	000	RW	ESR_EL1	ESR_EL1
11	000	0101	0010	000	RW	ESR_EL1	ESR_EL2
11	000	0101	0011	000	RO	ERRIDR_EL1	ERRIDR_EL1
11	000	0101	0011	001	RW	ERRSELR_EL1	ERRSELR_EL1
11	000	0101	0011	010	RO	ERXGSR_EL1	ERXGSR_EL1
11	000	0101	0100	000	RO	ERXFR_EL1	ERXFR_EL1
11	000	0101	0100	001	RW	ERXCTLR_EL1	ERXCTLR_EL1
11	000	0101	0100	010	RW	ERXSTATUS_EL1	ERXSTATUS_EL1
11	000	0101	0100	011	RW	ERXADDR_EL1	ERXADDR_EL1
11	000	0101	0100	100	RO	ERXPFGF_EL1	ERXPFGF_EL1
11	000	0101	0100	101	RW	ERXPFGCTL_EL1	ERXPFGCTL_EL1
11	000	0101	0100	110	RW	ERXPFGCDN_EL1	ERXPFGCDN_EL1
11	000	0101	0101	000	RW	ERXMISC0_EL1	ERXMISC0_EL1
11	000	0101	0101	001	RW	ERXMISC1_EL1	ERXMISC1_EL1
11	000	0101	0101	010	RW	ERXMISC2_EL1	ERXMISC2_EL1
11	000	0101	0101	011	RW	ERXMISC3_EL1	ERXMISC3_EL1
11	000	0101	0110	000	RW	TFSR_EL1	TFSR_EL1
11	000	0101	0110	000	RW	TFSR_EL1	TFSR_EL2
11	000	0101	0110	000	RW	TFSR_EL1	TFSR_EL1
11	000	0101	0110	000	RW	TFSR_EL1	TFSR_EL2
11	000	0101	0110	001	RW	TFSRE0_EL1	TFSRE0_EL1
11	000	0110	0000	000	RW	FAR_EL1	FAR_EL1
11	000	0110	0000	000	RW	FAR_EL1	FAR_EL2
11	000	0110	0000	000	RW	FAR_EL1	FAR_EL1
11	000	0110	0000	000	RW	FAR_EL1	FAR_EL2
11	000	0110	0000	101	RW	PFAR_EL1	PFAR_EL1
11	000	0110	0000	101	RW	PFAR_EL1	PFAR_EL2
11	000	0111	0100	000	RW	PAR_EL1	PAR_EL1
11	000	1001	1001	000	RW	PMSCR_EL1	PMSCR_EL1
11	000	1001	1001	000	RW	PMSCR_EL1	PMSCR_EL2
11	000	1001	1001	000	RW	PMSCR_EL1	PMSCR_EL1
11	000	1001	1001	000	RW	PMSCR_EL1	PMSCR_EL2
11	000	1001	1001	001	RW	PMSNEVFR_EL1	PMSNEVFR_EL1
11	000	1001	1001	010	RW	PMSICR_EL1	PMSICR_EL1
11	000	1001	1001	011	RW	PMSIRR_EL1	PMSIRR_EL1
11	000	1001	1001	100	RW	PMSFCR_EL1	PMSFCR_EL1
11	000	1001	1001	101	RW	PMSEVFR_EL1	PMSEVFR_EL1
11	000	1001	1001	110	RW	PMSLATFR_EL1	PMSLATFR_EL1
11	000	1001	1001	111	RO	PMSIDR_EL1	PMSIDR_EL1
11	000	1001	1010	000	RW	PMBLIMITR_EL1	PMBLIMITR_EL1
11	000	1001	1010	001	RW	PMBPTR_EL1	PMBPTR_EL1
11	000	1001	1010	011	RW	PMBSR_EL1	PMBSR_EL1
11	000	1001	1010	100	RW	PMSDSFR_EL1	PMSDSFR_EL1
11	000	1001	1010	111	RO	PMBIDR_EL1	PMBIDR_EL1
11	000	1001	1011	000	RW	TRBLIMITR_EL1	TRBLIMITR_EL1
11	000	1001	1011	001	RW	TRBPTR_EL1	TRBPTR_EL1
11	000	1001	1011	010	RW	TRBBASER_EL1	TRBBASER_EL1
11	000	1001	1011	011	RW	TRBSR_EL1	TRBSR_EL1
11	000	1001	1011	100	RW	TRBMAR_EL1	TRBMAR_EL1
11	000	1001	1011	101	RW	TRBMPAM_EL1	TRBMPAM_EL1
11	000	1001	1011	110	RW	TRBTRG_EL1	TRBTRG_EL1
11	000	1001	1011	111	RO	TRBIDR_EL1	TRBIDR_EL1
11	000	1001	1101	011	RW	PMSSCR_EL1	PMSSCR_EL1
11	000	1001	1110	001	RW	PMINTENSET_EL1	PMINTENSET_EL1
11	000	1001	1110	010	RW	PMINTENCLR_EL1	PMINTENCLR_EL1
11	000	1001	1110	100	RW	PMUACR_EL1	PMUACR_EL1
11	000	1001	1110	101	RW	PMECR_EL1	PMECR_EL1
11	000	1001	1110	110	RO	PMMIR_EL1	PMMIR_EL1
11	000	1001	1110	111	RW	PMIAR_EL1	PMIAR_EL1
11	000	1010	0010	000	RW	MAIR_EL1	MAIR_EL1
11	000	1010	0010	000	RW	MAIR_EL1	MAIR_EL2
11	000	1010	0010	000	RW	MAIR_EL1	MAIR_EL1
11	000	1010	0010	000	RW	MAIR_EL1	MAIR_EL2
11	000	1010	0010	001	RW	MAIR2_EL1	MAIR2_EL1
11	000	1010	0010	001	RW	MAIR2_EL1	MAIR2_EL2
11	000	1010	0010	001	RW	MAIR2_EL1	MAIR2_EL1
11	000	1010	0010	001	RW	MAIR2_EL1	MAIR2_EL2
11	000	1010	0010	010	RW	PIRE0_EL1	PIRE0_EL1
11	000	1010	0010	010	RW	PIRE0_EL1	PIRE0_EL2
11	000	1010	0010	010	RW	PIRE0_EL1	PIRE0_EL1
11	000	1010	0010	010	RW	PIRE0_EL1	PIRE0_EL2
11	000	1010	0010	011	RW	PIR_EL1	PIR_EL1
11	000	1010	0010	011	RW	PIR_EL1	PIR_EL2
11	000	1010	0010	011	RW	PIR_EL1	PIR_EL1
11	000	1010	0010	011	RW	PIR_EL1	PIR_EL2
11	000	1010	0010	100	RW	POR_EL1	POR_EL1
11	000	1010	0010	100	RW	POR_EL1	POR_EL2
11	000	1010	0010	100	RW	POR_EL1	POR_EL1
11	000	1010	0010	100	RW	POR_EL1	POR_EL2
11	000	1010	0010	101	RW	S2POR_EL1	S2POR_EL1
11	000	1010	0011	000	RW	AMAIR_EL1	AMAIR_EL1
11	000	1010	0011	000	RW	AMAIR_EL1	AMAIR_EL2
11	000	1010	0011	000	RW	AMAIR_EL1	AMAIR_EL1
11	000	1010	0011	000	RW	AMAIR_EL1	AMAIR_EL2
11	000	1010	0011	001	RW	AMAIR2_EL1	AMAIR2_EL1
11	000	1010	0011	001	RW	AMAIR2_EL1	AMAIR2_EL2
11	000	1010	0011	001	RW	AMAIR2_EL1	AMAIR2_EL1
11	000	1010	0011	001	RW	AMAIR2_EL1	AMAIR2_EL2
11	000	1010	0100	000	RW	LORSA_EL1	LORSA_EL1
11	000	1010	0100	001	RW	LOREA_EL1	LOREA_EL1
11	000	1010	0100	010	RW	LORN_EL1	LORN_EL1
11	000	1010	0100	011	RW	LORC_EL1	LORC_EL1
11	000	1010	0100	100	RO	MPAMIDR_EL1	MPAMIDR_EL1
11	000	1010	0100	111	RO	LORID_EL1	LORID_EL1
11	000	1010	0101	000	RW	MPAM1_EL1	MPAM1_EL1
11	000	1010	0101	000	RW	MPAM1_EL1	MPAM2_EL2
11	000	1010	0101	000	RW	MPAM1_EL1	MPAM1_EL1
11	000	1010	0101	000	RW	MPAM1_EL1	MPAM2_EL2
11	000	1010	0101	001	RW	MPAM0_EL1	MPAM0_EL1
11	000	1010	0101	011	RW	MPAMSM_EL1	MPAMSM_EL1
11	000	1100	0000	000	RW	VBAR_EL1	VBAR_EL1
11	000	1100	0000	000	RW	VBAR_EL1	VBAR_EL2
11	000	1100	0000	000	RW	VBAR_EL1	VBAR_EL1
11	000	1100	0000	000	RW	VBAR_EL1	VBAR_EL2
11	000	1100	0000	001	RO	RVBAR_EL1	RVBAR_EL1
11	000	1100	0000	010	RW	RMR_EL1	RMR_EL1
11	000	1100	0001	000	RO	ISR_EL1	ISR_EL1
11	000	1100	0001	001	RW	DISR_EL1	DISR_EL1
11	000	1100	0001	001	RW	DISR_EL1	VDISR_EL2
11	000	1100	0001	001	RW	DISR_EL1	DISR_EL1
11	000	1100	0001	001	RW	DISR_EL1	VDISR_EL2
11	000	1100	1000	000	RO	ICC_IAR0_EL1	ICC_IAR0_EL1
11	000	1100	1000	000	RO	ICC_IAR0_EL1	ICV_IAR0_EL1
11	000	1100	1000	000	RO	ICC_IAR0_EL1	ICC_IAR0_EL1
11	000	1100	1000	000	RO	ICC_IAR0_EL1	ICV_IAR0_EL1
11	000	1100	1000	001	WO	ICC_EOIR0_EL1	ICC_EOIR0_EL1
11	000	1100	1000	001	WO	ICC_EOIR0_EL1	ICV_EOIR0_EL1
11	000	1100	1000	001	WO	ICC_EOIR0_EL1	ICC_EOIR0_EL1
11	000	1100	1000	001	WO	ICC_EOIR0_EL1	ICV_EOIR0_EL1
11	000	1100	1000	010	RO	ICC_HPPIR0_EL1	ICC_HPPIR0_EL1
11	000	1100	1000	010	RO	ICC_HPPIR0_EL1	ICV_HPPIR0_EL1
11	000	1100	1000	010	RO	ICC_HPPIR0_EL1	ICC_HPPIR0_EL1
11	000	1100	1000	010	RO	ICC_HPPIR0_EL1	ICV_HPPIR0_EL1
11	000	1100	1000	011	RW	ICC_BPR0_EL1	ICC_BPR0_EL1
11	000	1100	1000	011	RW	ICC_BPR0_EL1	ICV_BPR0_EL1
11	000	1100	1000	011	RW	ICC_BPR0_EL1	ICC_BPR0_EL1
11	000	1100	1000	011	RW	ICC_BPR0_EL1	ICV_BPR0_EL1
11	000	1100	1000	1:m[1:0]	RW	ICC_AP0R<m>_EL1	ICC_AP0R_EL1[]
11	000	1100	1000	1:m[1:0]	RW	ICC_AP0R<m>_EL1	ICV_AP0R_EL1[]
11	000	1100	1000	1:m[1:0]	RW	ICC_AP0R<m>_EL1	ICC_AP0R_EL1[]
11	000	1100	1000	1:m[1:0]	RW	ICC_AP0R<m>_EL1	ICV_AP0R_EL1[]
11	000	1100	1001	0:m[1:0]	RW	ICC_AP1R<m>_EL1	ICC_AP1R_EL1[]
11	000	1100	1001	0:m[1:0]	RW	ICC_AP1R<m>_EL1	ICC_AP1R_EL1_NS[]
11	000	1100	1001	0:m[1:0]	RW	ICC_AP1R<m>_EL1	ICC_AP1R_EL1_S[]
11	000	1100	1001	0:m[1:0]	RW	ICC_AP1R<m>_EL1	ICV_AP1R_EL1[]
11	000	1100	1001	0:m[1:0]	RW	ICC_AP1R<m>_EL1	ICC_AP1R_EL1[]
11	000	1100	1001	0:m[1:0]	RW	ICC_AP1R<m>_EL1	ICC_AP1R_EL1_NS[]
11	000	1100	1001	0:m[1:0]	RW	ICC_AP1R<m>_EL1	ICC_AP1R_EL1_S[]
11	000	1100	1001	0:m[1:0]	RW	ICC_AP1R<m>_EL1	ICV_AP1R_EL1[]
11	000	1100	1001	101	RO	ICC_NMIAR1_EL1	ICC_NMIAR1_EL1
11	000	1100	1001	101	RO	ICC_NMIAR1_EL1	ICV_NMIAR1_EL1
11	000	1100	1001	101	RO	ICC_NMIAR1_EL1	ICC_NMIAR1_EL1
11	000	1100	1001	101	RO	ICC_NMIAR1_EL1	ICV_NMIAR1_EL1
11	000	1100	1011	001	WO	ICC_DIR_EL1	ICC_DIR_EL1
11	000	1100	1011	001	WO	ICC_DIR_EL1	ICV_DIR_EL1
11	000	1100	1011	001	WO	ICC_DIR_EL1	ICC_DIR_EL1
11	000	1100	1011	001	WO	ICC_DIR_EL1	ICV_DIR_EL1
11	000	1100	1011	011	RO	ICC_RPR_EL1	ICC_RPR_EL1
11	000	1100	1011	011	RO	ICC_RPR_EL1	ICV_RPR_EL1
11	000	1100	1011	011	RO	ICC_RPR_EL1	ICC_RPR_EL1
11	000	1100	1011	011	RO	ICC_RPR_EL1	ICV_RPR_EL1
11	000	1100	1011	101	WO	ICC_SGI1R_EL1	ICC_SGI1R_EL1
11	000	1100	1011	110	WO	ICC_ASGI1R_EL1	ICC_ASGI1R_EL1
11	000	1100	1011	111	WO	ICC_SGI0R_EL1	ICC_SGI0R_EL1
11	000	1100	1100	000	RO	ICC_IAR1_EL1	ICC_IAR1_EL1
11	000	1100	1100	000	RO	ICC_IAR1_EL1	ICV_IAR1_EL1
11	000	1100	1100	000	RO	ICC_IAR1_EL1	ICC_IAR1_EL1
11	000	1100	1100	000	RO	ICC_IAR1_EL1	ICV_IAR1_EL1
11	000	1100	1100	001	WO	ICC_EOIR1_EL1	ICC_EOIR1_EL1
11	000	1100	1100	001	WO	ICC_EOIR1_EL1	ICV_EOIR1_EL1
11	000	1100	1100	001	WO	ICC_EOIR1_EL1	ICC_EOIR1_EL1
11	000	1100	1100	001	WO	ICC_EOIR1_EL1	ICV_EOIR1_EL1
11	000	1100	1100	010	RO	ICC_HPPIR1_EL1	ICC_HPPIR1_EL1
11	000	1100	1100	010	RO	ICC_HPPIR1_EL1	ICV_HPPIR1_EL1
11	000	1100	1100	010	RO	ICC_HPPIR1_EL1	ICC_HPPIR1_EL1
11	000	1100	1100	010	RO	ICC_HPPIR1_EL1	ICV_HPPIR1_EL1
11	000	1100	1100	011	RW	ICC_BPR1_EL1	ICC_BPR1_EL1
11	000	1100	1100	011	RW	ICC_BPR1_EL1	ICC_BPR1_EL1_NS
11	000	1100	1100	011	RW	ICC_BPR1_EL1	ICC_BPR1_EL1_S
11	000	1100	1100	011	RW	ICC_BPR1_EL1	ICV_BPR1_EL1
11	000	1100	1100	011	RW	ICC_BPR1_EL1	ICC_BPR1_EL1
11	000	1100	1100	011	RW	ICC_BPR1_EL1	ICC_BPR1_EL1_NS
11	000	1100	1100	011	RW	ICC_BPR1_EL1	ICC_BPR1_EL1_S
11	000	1100	1100	011	RW	ICC_BPR1_EL1	ICV_BPR1_EL1
11	000	1100	1100	100	RW	ICC_CTLR_EL1	ICC_CTLR_EL1
11	000	1100	1100	100	RW	ICC_CTLR_EL1	ICC_CTLR_EL1_NS
11	000	1100	1100	100	RW	ICC_CTLR_EL1	ICC_CTLR_EL1_S
11	000	1100	1100	100	RW	ICC_CTLR_EL1	ICV_CTLR_EL1
11	000	1100	1100	100	RW	ICC_CTLR_EL1	ICC_CTLR_EL1
11	000	1100	1100	100	RW	ICC_CTLR_EL1	ICC_CTLR_EL1_NS
11	000	1100	1100	100	RW	ICC_CTLR_EL1	ICC_CTLR_EL1_S
11	000	1100	1100	100	RW	ICC_CTLR_EL1	ICV_CTLR_EL1
11	000	1100	1100	101	RW	ICC_SRE_EL1	ICC_SRE_EL1
11	000	1100	1100	101	RW	ICC_SRE_EL1	ICC_SRE_EL1_NS
11	000	1100	1100	101	RW	ICC_SRE_EL1	ICC_SRE_EL1_S
11	000	1100	1100	110	RW	ICC_IGRPEN0_EL1	ICC_IGRPEN0_EL1
11	000	1100	1100	110	RW	ICC_IGRPEN0_EL1	ICV_IGRPEN0_EL1
11	000	1100	1100	110	RW	ICC_IGRPEN0_EL1	ICC_IGRPEN0_EL1
11	000	1100	1100	110	RW	ICC_IGRPEN0_EL1	ICV_IGRPEN0_EL1
11	000	1100	1100	111	RW	ICC_IGRPEN1_EL1	ICC_IGRPEN1_EL1
11	000	1100	1100	111	RW	ICC_IGRPEN1_EL1	ICC_IGRPEN1_EL1_NS
11	000	1100	1100	111	RW	ICC_IGRPEN1_EL1	ICC_IGRPEN1_EL1_S
11	000	1100	1100	111	RW	ICC_IGRPEN1_EL1	ICV_IGRPEN1_EL1
11	000	1100	1100	111	RW	ICC_IGRPEN1_EL1	ICC_IGRPEN1_EL1
11	000	1100	1100	111	RW	ICC_IGRPEN1_EL1	ICC_IGRPEN1_EL1_NS
11	000	1100	1100	111	RW	ICC_IGRPEN1_EL1	ICC_IGRPEN1_EL1_S
11	000	1100	1100	111	RW	ICC_IGRPEN1_EL1	ICV_IGRPEN1_EL1
11	000	1101	0000	001	RW	CONTEXTIDR_EL1	CONTEXTIDR_EL1
11	000	1101	0000	001	RW	CONTEXTIDR_EL1	CONTEXTIDR_EL2
11	000	1101	0000	001	RW	CONTEXTIDR_EL1	CONTEXTIDR_EL1
11	000	1101	0000	001	RW	CONTEXTIDR_EL1	CONTEXTIDR_EL2
11	000	1101	0000	011	RW	RCWSMASK_EL1	RCWSMASK_EL1
11	000	1101	0000	100	RW	TPIDR_EL1	TPIDR_EL1
11	000	1101	0000	101	RW	ACCDATA_EL1	ACCDATA_EL1
11	000	1101	0000	110	RW	RCWMASK_EL1	RCWMASK_EL1
11	000	1101	0000	111	RW	SCXTNUM_EL1	SCXTNUM_EL1
11	000	1101	0000	111	RW	SCXTNUM_EL1	SCXTNUM_EL2
11	000	1101	0000	111	RW	SCXTNUM_EL1	SCXTNUM_EL1
11	000	1101	0000	111	RW	SCXTNUM_EL1	SCXTNUM_EL2
11	000	1110	0001	000	RW	CNTKCTL_EL1	CNTHCTL_EL2
11	000	1110	0001	000	RW	CNTKCTL_EL1	CNTKCTL_EL1
11	000	1110	0001	000	RW	CNTKCTL_EL1	CNTHCTL_EL2
11	000	1110	0001	000	RW	CNTKCTL_EL1	CNTKCTL_EL1
11	001	0000	0000	000	RO	CCSIDR_EL1	CCSIDR_EL1
11	001	0000	0000	001	RO	CLIDR_EL1	CLIDR_EL1
11	001	0000	0000	010	RO	CCSIDR2_EL1	CCSIDR2_EL1
11	001	0000	0000	100	RO	GMID_EL1	GMID_EL1
11	001	0000	0000	110	RO	SMIDR_EL1	SMIDR_EL1
11	001	0000	0000	111	RO	AIDR_EL1	AIDR_EL1
11	010	0000	0000	000	RW	CSSELR_EL1	CSSELR_EL1
11	011	0000	0000	001	RO	CTR_EL0	CTR_EL0
11	011	0000	0000	111	RO	DCZID_EL0	DCZID_EL0
11	011	0010	0100	000	RO	RNDR	RNDR
11	011	0010	0100	001	RO	RNDRRS	RNDRRS
11	011	0010	0101	001	RW	GCSPR_EL0	GCSPR_EL0
11	011	0100	0010	000	-	NZCV	-
11	011	0100	0010	001	-	DAIF	-
11	011	0100	0010	010	-	SVCR	-
11	011	0100	0010	101	-	DIT	-
11	011	0100	0010	110	-	SSBS	-
11	011	0100	0010	111	-	TCO	-
11	011	0100	0100	000	RW	FPCR	FPCR
11	011	0100	0100	001	RW	FPSR	FPSR
11	011	0100	0101	000	RW	DSPSR_EL0	DSPSR_EL0
11	011	0100	0101	001	RW	DLR_EL0	DLR_EL0
11	011	1001	0100	000	RW	PMICNTR_EL0	PMICNTR_EL0
11	011	1001	0110	000	RW	PMICFILTR_EL0	PMICFILTR_EL0
11	011	1001	1100	000	RW	PMCR_EL0	PMCR_EL0
11	011	1001	1100	001	RW	PMCNTENSET_EL0	PMCNTENSET_EL0
11	011	1001	1100	010	RW	PMCNTENCLR_EL0	PMCNTENCLR_EL0
11	011	1001	1100	011	RW	PMOVSCLR_EL0	PMOVSCLR_EL0
11	011	1001	1100	100	WO	PMSWINC_EL0	PMSWINC_EL0
11	011	1001	1100	101	RW	PMSELR_EL0	PMSELR_EL0
11	011	1001	1100	110	RO	PMCEID0_EL0	PMCEID0_EL0
11	011	1001	1100	111	RO	PMCEID1_EL0	PMCEID1_EL0
11	011	1001	1101	000	RW	PMCCNTR_EL0	PMCCNTR_EL0
11	011	1001	1101	001	RW	PMXEVTYPER_EL0	PMCCFILTR_EL0
11	011	1001	1101	001	RW	PMXEVTYPER_EL0	PMEVTYPER_EL0
11	011	1001	1101	010	RW	PMXEVCNTR_EL0	PMEVCNTR_EL0
11	011	1001	1101	100	WO	PMZR_EL0	PMZR_EL0
11	011	1001	1110	000	RW	PMUSERENR_EL0	PMUSERENR_EL0
11	011	1001	1110	011	RW	PMOVSSET_EL0	PMOVSSET_EL0
11	011	1010	0010	100	RW	POR_EL0	POR_EL0
11	011	1101	0000	010	RW	TPIDR_EL0	TPIDR_EL0
11	011	1101	0000	011	RW	TPIDRRO_EL0	TPIDRRO_EL0
11	011	1101	0000	101	RW	TPIDR2_EL0	TPIDR2_EL0
11	011	1101	0000	111	RW	SCXTNUM_EL0	SCXTNUM_EL0
11	011	1101	0010	000	RW	AMCR_EL0	AMCR_EL0
11	011	1101	0010	001	RO	AMCFGR_EL0	AMCFGR_EL0
11	011	1101	0010	010	RO	AMCGCR_EL0	AMCGCR_EL0
11	011	1101	0010	011	RW	AMUSERENR_EL0	AMUSERENR_EL0
11	011	1101	0010	100	RW	AMCNTENCLR0_EL0	AMCNTENCLR0_EL0
11	011	1101	0010	101	RW	AMCNTENSET0_EL0	AMCNTENSET0_EL0
11	011	1101	0010	110	RO	AMCG1IDR_EL0	AMCG1IDR_EL0
11	011	1101	0011	000	RW	AMCNTENCLR1_EL0	AMCNTENCLR1_EL0
11	011	1101	0011	001	RW	AMCNTENSET1_EL0	AMCNTENSET1_EL0
11	011	1101	010:m[3]	m[2:0]	RW	AMEVCNTR0<m>_EL0	AMEVCNTR0_EL0[]
11	011	1101	011:m[3]	m[2:0]	RO	AMEVTYPER0<m>_EL0	AMEVTYPER0_EL0[]
11	011	1101	110:m[3]	m[2:0]	RW	AMEVCNTR1<m>_EL0	AMEVCNTR1_EL0[]
11	011	1101	111:m[3]	m[2:0]	RW	AMEVTYPER1<m>_EL0	AMEVTYPER1_EL0[]
11	011	1110	0000	000	RW	CNTFRQ_EL0	CNTFRQ_EL0
11	011	1110	0000	001	-	CNTPCT_EL0	-
11	011	1110	0000	010	-	CNTVCT_EL0	-
11	011	1110	0000	101	-	CNTPCTSS_EL0	-
11	011	1110	0000	110	-	CNTVCTSS_EL0	-
11	011	1110	0010	000	-	CNTP_TVAL_EL0	-
11	011	1110	0010	000	-	CNTP_TVAL_EL0	-
11	011	1110	0010	000	-	CNTP_TVAL_EL0	-
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTHPS_CTL_EL2
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTHP_CTL_EL2
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTP_CTL_EL0
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTHPS_CTL_EL2
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTHP_CTL_EL2
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTP_CTL_EL0
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTHPS_CTL_EL2
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTHP_CTL_EL2
11	011	1110	0010	001	RW	CNTP_CTL_EL0	CNTP_CTL_EL0
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTHPS_CVAL_EL2
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTHP_CVAL_EL2
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTP_CVAL_EL0
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTHPS_CVAL_EL2
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTHP_CVAL_EL2
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTP_CVAL_EL0
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTHPS_CVAL_EL2
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTHP_CVAL_EL2
11	011	1110	0010	010	RW	CNTP_CVAL_EL0	CNTP_CVAL_EL0
11	011	1110	0011	000	-	CNTV_TVAL_EL0	-
11	011	1110	0011	000	-	CNTV_TVAL_EL0	-
11	011	1110	0011	000	-	CNTV_TVAL_EL0	-
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTHVS_CTL_EL2
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTHV_CTL_EL2
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTV_CTL_EL0
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTHVS_CTL_EL2
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTHV_CTL_EL2
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTV_CTL_EL0
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTHVS_CTL_EL2
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTHV_CTL_EL2
11	011	1110	0011	001	RW	CNTV_CTL_EL0	CNTV_CTL_EL0
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTHVS_CVAL_EL2
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTHV_CVAL_EL2
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTV_CVAL_EL0
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTHVS_CVAL_EL2
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTHV_CVAL_EL2
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTV_CVAL_EL0
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTHVS_CVAL_EL2
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTHV_CVAL_EL2
11	011	1110	0011	010	RW	CNTV_CVAL_EL0	CNTV_CVAL_EL0
11	011	1110	10:m[4:3]	m[2:0]	RW	PMEVCNTR<m>_EL0	PMEVCNTR_EL0[]
11	011	1110	1111	111	RW	PMCCFILTR_EL0	PMCCFILTR_EL0
11	011	1110	11:m[4:3]	m[2:0]	RW	PMEVTYPER<m>_EL0	PMEVTYPER_EL0[]
11	100	0000	0000	000	RO	VPIDR_EL2	MIDR_EL1
11	100	0000	0000	000	RW	VPIDR_EL2	VPIDR_EL2
11	100	0000	0000	101	RO	VMPIDR_EL2	MPIDR_EL1
11	100	0000	0000	101	RW	VMPIDR_EL2	VMPIDR_EL2
11	100	0001	0000	000	RW	SCTLR_EL2	SCTLR_EL2
11	100	0001	0000	001	RW	ACTLR_EL2	ACTLR_EL2
11	100	0001	0000	011	RW	SCTLR2_EL2	SCTLR2_EL2
11	100	0001	0001	000	RW	HCR_EL2	HCR_EL2
11	100	0001	0001	001	RW	MDCR_EL2	MDCR_EL2
11	100	0001	0001	010	RW	CPTR_EL2	CPTR_EL2
11	100	0001	0001	011	RW	HSTR_EL2	HSTR_EL2
11	100	0001	0001	100	RW	HFGRTR_EL2	HFGRTR_EL2
11	100	0001	0001	101	RW	HFGWTR_EL2	HFGWTR_EL2
11	100	0001	0001	110	RW	HFGITR_EL2	HFGITR_EL2
11	100	0001	0001	111	RW	HACR_EL2	HACR_EL2
11	100	0001	0010	000	RW	ZCR_EL2	ZCR_EL2
11	100	0001	0010	001	RW	TRFCR_EL2	TRFCR_EL2
11	100	0001	0010	010	RW	HCRX_EL2	HCRX_EL2
11	100	0001	0010	011	RW	TRCITECR_EL2	TRCITECR_EL2
11	100	0001	0010	101	RW	SMPRIMAP_EL2	SMPRIMAP_EL2
11	100	0001	0010	110	RW	SMCR_EL2	SMCR_EL2
11	100	0001	0011	001	RW	SDER32_EL2	SDER32_EL2
11	100	0010	0000	000	RW	TTBR0_EL2	TTBR0_EL2
11	100	0010	0000	001	RW	TTBR1_EL2	TTBR1_EL2
11	100	0010	0000	010	RW	TCR_EL2	TCR_EL2
11	100	0010	0000	011	RW	TCR2_EL2	TCR2_EL2
11	100	0010	0001	000	RW	VTTBR_EL2	VTTBR_EL2
11	100	0010	0001	010	RW	VTCR_EL2	VTCR_EL2
11	100	0010	0010	000	RW	VNCR_EL2	VNCR_EL2
11	100	0010	0101	000	RW	GCSCR_EL2	GCSCR_EL2
11	100	0010	0101	001	RW	GCSPR_EL2	GCSPR_EL2
11	100	0010	0110	000	RW	VSTTBR_EL2	VSTTBR_EL2
11	100	0010	0110	010	RW	VSTCR_EL2	VSTCR_EL2
11	100	0011	0000	000	RW	DACR32_EL2	DACR32_EL2
11	100	0011	0001	000	RW	HDFGRTR2_EL2	HDFGRTR2_EL2
11	100	0011	0001	001	RW	HDFGWTR2_EL2	HDFGWTR2_EL2
11	100	0011	0001	010	RW	HFGRTR2_EL2	HFGRTR2_EL2
11	100	0011	0001	011	RW	HFGWTR2_EL2	HFGWTR2_EL2
11	100	0011	0001	100	RW	HDFGRTR_EL2	HDFGRTR_EL2
11	100	0011	0001	101	RW	HDFGWTR_EL2	HDFGWTR_EL2
11	100	0011	0001	110	RW	HAFGRTR_EL2	HAFGRTR_EL2
11	100	0011	0001	111	RW	HFGITR2_EL2	HFGITR2_EL2
11	100	0100	0000	000	RW	SPSR_EL2	SPSR_EL1
11	100	0100	0000	000	RW	SPSR_EL2	SPSR_EL2
11	100	0100	0000	000	RW	SPSR_EL2	SPSR_EL1
11	100	0100	0000	000	RW	SPSR_EL2	SPSR_EL2
11	100	0100	0000	001	RW	ELR_EL2	ELR_EL1
11	100	0100	0000	001	RW	ELR_EL2	ELR_EL2
11	100	0100	0000	001	RW	ELR_EL2	ELR_EL1
11	100	0100	0000	001	RW	ELR_EL2	ELR_EL2
11	100	0100	0001	000	RW	SP_EL1	SP_EL1
11	100	0100	0011	000	RW	SPSR_irq	SPSR_irq
11	100	0100	0011	001	RW	SPSR_abt	SPSR_abt
11	100	0100	0011	010	RW	SPSR_und	SPSR_und
11	100	0100	0011	011	RW	SPSR_fiq	SPSR_fiq
11	100	0101	0000	001	RW	IFSR32_EL2	IFSR32_EL2
11	100	0101	0001	000	RW	AFSR0_EL2	AFSR0_EL2
11	100	0101	0001	001	RW	AFSR1_EL2	AFSR1_EL2
11	100	0101	0010	000	RW	ESR_EL2	ESR_EL1
11	100	0101	0010	000	RW	ESR_EL2	ESR_EL2
11	100	0101	0010	000	RW	ESR_EL2	ESR_EL1
11	100	0101	0010	000	RW	ESR_EL2	ESR_EL2
11	100	0101	0010	011	RW	VSESR_EL2	VSESR_EL2
11	100	0101	0011	000	RW	FPEXC32_EL2	FPEXC32_EL2
11	100	0101	0110	000	RW	TFSR_EL2	TFSR_EL1
11	100	0101	0110	000	RW	TFSR_EL2	TFSR_EL2
11	100	0101	0110	000	RW	TFSR_EL2	TFSR_EL1
11	100	0101	0110	000	RW	TFSR_EL2	TFSR_EL2
11	100	0110	0000	000	RW	FAR_EL2	FAR_EL1
11	100	0110	0000	000	RW	FAR_EL2	FAR_EL2
11	100	0110	0000	000	RW	FAR_EL2	FAR_EL1
11	100	0110	0000	000	RW	FAR_EL2	FAR_EL2
11	100	0110	0000	100	RW	HPFAR_EL2	HPFAR_EL2
11	100	0110	0000	101	RW	PFAR_EL2	PFAR_EL2
11	100	1001	1001	000	RW	PMSCR_EL2	PMSCR_EL2
11	100	1010	0001	001	RW	MAIR2_EL2	MAIR2_EL2
11	100	1010	0010	000	RW	MAIR_EL2	MAIR_EL2
11	100	1010	0010	010	RW	PIRE0_EL2	PIRE0_EL2
11	100	1010	0010	011	RW	PIR_EL2	PIR_EL2
11	100	1010	0010	100	RW	POR_EL2	POR_EL2
11	100	1010	0010	101	RW	S2PIR_EL2	S2PIR_EL2
11	100	1010	0011	000	RW	AMAIR_EL2	AMAIR_EL2
11	100	1010	0011	001	RW	AMAIR2_EL2	AMAIR2_EL2
11	100	1010	0100	000	RW	MPAMHCR_EL2	MPAMHCR_EL2
11	100	1010	0100	001	RW	MPAMVPMV_EL2	MPAMVPMV_EL2
11	100	1010	0101	000	RW	MPAM2_EL2	MPAM2_EL2
11	100	1010	0110	000	RW	MPAMVPM0_EL2	MPAMVPM0_EL2
11	100	1010	0110	001	RW	MPAMVPM1_EL2	MPAMVPM1_EL2
11	100	1010	0110	010	RW	MPAMVPM2_EL2	MPAMVPM2_EL2
11	100	1010	0110	011	RW	MPAMVPM3_EL2	MPAMVPM3_EL2
11	100	1010	0110	100	RW	MPAMVPM4_EL2	MPAMVPM4_EL2
11	100	1010	0110	101	RW	MPAMVPM5_EL2	MPAMVPM5_EL2
11	100	1010	0110	110	RW	MPAMVPM6_EL2	MPAMVPM6_EL2
11	100	1010	0110	111	RW	MPAMVPM7_EL2	MPAMVPM7_EL2
11	100	1010	1000	000	RW	MECID_P0_EL2	MECID_P0_EL2
11	100	1010	1000	001	RW	MECID_A0_EL2	MECID_A0_EL2
11	100	1010	1000	010	RW	MECID_P1_EL2	MECID_P1_EL2
11	100	1010	1000	011	RW	MECID_A1_EL2	MECID_A1_EL2
11	100	1010	1000	111	RO	MECIDR_EL2	MECIDR_EL2
11	100	1010	1001	000	RW	VMECID_P_EL2	VMECID_P_EL2
11	100	1010	1001	001	RW	VMECID_A_EL2	VMECID_A_EL2
11	100	1100	0000	000	RW	VBAR_EL2	VBAR_EL2
11	100	1100	0000	001	RO	RVBAR_EL2	RVBAR_EL2
11	100	1100	0000	010	RW	RMR_EL2	RMR_EL2
11	100	1100	0001	001	RW	VDISR_EL2	VDISR_EL2
11	100	1100	1000	0:m[1:0]	RW	ICH_AP0R<m>_EL2	ICH_AP0R_EL2[]
11	100	1100	1001	0:m[1:0]	RW	ICH_AP1R<m>_EL2	ICH_AP1R_EL2[]
11	100	1100	1001	101	RW	ICC_SRE_EL2	ICC_SRE_EL2
11	100	1100	1011	000	RW	ICH_HCR_EL2	ICH_HCR_EL2
11	100	1100	1011	001	RO	ICH_VTR_EL2	ICH_VTR_EL2
11	100	1100	1011	010	RO	ICH_MISR_EL2	ICH_MISR_EL2
11	100	1100	1011	011	RO	ICH_EISR_EL2	ICH_EISR_EL2
11	100	1100	1011	101	RO	ICH_ELRSR_EL2	ICH_ELRSR_EL2
11	100	1100	1011	111	RW	ICH_VMCR_EL2	ICH_VMCR_EL2
11	100	1100	110:m[3]	m[2:0]	RW	ICH_LR<m>_EL2	ICH_LR_EL2[]
11	100	1101	0000	001	RW	CONTEXTIDR_EL2	CONTEXTIDR_EL2
11	100	1101	0000	010	RW	TPIDR_EL2	TPIDR_EL2
11	100	1101	0000	111	RW	SCXTNUM_EL2	SCXTNUM_EL2
11	100	1101	100:m[3]	m[2:0]	RW	AMEVCNTVOFF0<m>_EL2	AMEVCNTVOFF0_EL2[]
11	100	1101	101:m[3]	m[2:0]	RW	AMEVCNTVOFF1<m>_EL2	AMEVCNTVOFF1_EL2[]
11	100	1110	0000	011	RW	CNTVOFF_EL2	CNTVOFF_EL2
11	100	1110	0000	110	RW	CNTPOFF_EL2	CNTPOFF_EL2
11	100	1110	0001	000	RW	CNTHCTL_EL2	CNTHCTL_EL2
11	100	1110	0010	000	-	CNTHP_TVAL_EL2	-
11	100	1110	0010	001	RW	CNTHP_CTL_EL2	CNTHP_CTL_EL2
11	100	1110	0010	010	RW	CNTHP_CVAL_EL2	CNTHP_CVAL_EL2
11	100	1110	0011	000	-	CNTHV_TVAL_EL2	-
11	100	1110	0011	001	RW	CNTHV_CTL_EL2	CNTHV_CTL_EL2
11	100	1110	0011	010	RW	CNTHV_CVAL_EL2	CNTHV_CVAL_EL2
11	100	1110	0100	000	-	CNTHVS_TVAL_EL2	-
11	100	1110	0100	001	RW	CNTHVS_CTL_EL2	CNTHVS_CTL_EL2
11	100	1110	0100	010	RW	CNTHVS_CVAL_EL2	CNTHVS_CVAL_EL2
11	100	1110	0101	000	-	CNTHPS_TVAL_EL2	-
11	100	1110	0101	001	RW	CNTHPS_CTL_EL2	CNTHPS_CTL_EL2
11	100	1110	0101	010	RW	CNTHPS_CVAL_EL2	CNTHPS_CVAL_EL2
11	101	0001	0000	000	RW	SCTLR_EL12	SCTLR_EL1
11	101	0001	0000	010	RW	CPACR_EL12	CPACR_EL1
11	101	0001	0000	011	RW	SCTLR2_EL12	SCTLR2_EL1
11	101	0001	0010	000	RW	ZCR_EL12	ZCR_EL1
11	101	0001	0010	001	RW	TRFCR_EL12	TRFCR_EL1
11	101	0001	0010	011	RW	TRCITECR_EL12	TRCITECR_EL1
11	101	0001	0010	110	RW	SMCR_EL12	SMCR_EL1
11	101	0010	0000	000	RW	TTBR0_EL12	TTBR0_EL1
11	101	0010	0000	001	RW	TTBR1_EL12	TTBR1_EL1
11	101	0010	0000	010	RW	TCR_EL12	TCR_EL1
11	101	0010	0000	011	RW	TCR2_EL12	TCR2_EL1
11	101	0010	0101	000	RW	GCSCR_EL12	GCSCR_EL1
11	101	0010	0101	001	RW	GCSPR_EL12	GCSPR_EL1
11	101	0100	0000	000	RW	SPSR_EL12	SPSR_EL1
11	101	0100	0000	001	RW	ELR_EL12	ELR_EL1
11	101	0101	0001	000	RW	AFSR0_EL12	AFSR0_EL1
11	101	0101	0001	001	RW	AFSR1_EL12	AFSR1_EL1
11	101	0101	0010	000	RW	ESR_EL12	ESR_EL1
11	101	0101	0110	000	RW	TFSR_EL12	TFSR_EL1
11	101	0110	0000	000	RW	FAR_EL12	FAR_EL1
11	101	0110	0000	101	RW	PFAR_EL12	PFAR_EL1
11	101	1001	1001	000	RW	PMSCR_EL12	PMSCR_EL1
11	101	1010	0010	000	RW	MAIR_EL12	MAIR_EL1
11	101	1010	0010	001	RW	MAIR2_EL12	MAIR2_EL1
11	101	1010	0010	010	RW	PIRE0_EL12	PIRE0_EL1
11	101	1010	0010	011	RW	PIR_EL12	PIR_EL1
11	101	1010	0010	100	RW	POR_EL12	POR_EL1
11	101	1010	0011	000	RW	AMAIR_EL12	AMAIR_EL1
11	101	1010	0011	001	RW	AMAIR2_EL12	AMAIR2_EL1
11	101	1010	0101	000	RW	MPAM1_EL12	MPAM1_EL1
11	101	1100	0000	000	RW	VBAR_EL12	VBAR_EL1
11	101	1101	0000	001	RW	CONTEXTIDR_EL12	CONTEXTIDR_EL1
11	101	1101	0000	111	RW	SCXTNUM_EL12	SCXTNUM_EL1
11	101	1110	0001	000	RW	CNTKCTL_EL12	CNTKCTL_EL1
11	101	1110	0010	000	-	CNTP_TVAL_EL02	-
11	101	1110	0010	001	RW	CNTP_CTL_EL02	CNTP_CTL_EL0
11	101	1110	0010	010	RW	CNTP_CVAL_EL02	CNTP_CVAL_EL0
11	101	1110	0011	000	-	CNTV_TVAL_EL02	-
11	101	1110	0011	001	RW	CNTV_CTL_EL02	CNTV_CTL_EL0
11	101	1110	0011	010	RW	CNTV_CVAL_EL02	CNTV_CVAL_EL0
11	110	0001	0000	000	RW	SCTLR_EL3	SCTLR_EL3
11	110	0001	0000	001	RW	ACTLR_EL3	ACTLR_EL3
11	110	0001	0000	011	RW	SCTLR2_EL3	SCTLR2_EL3
11	110	0001	0001	000	RW	SCR_EL3	SCR_EL3
11	110	0001	0001	001	RW	SDER32_EL3	SDER32_EL3
11	110	0001	0001	010	RW	CPTR_EL3	CPTR_EL3
11	110	0001	0010	000	RW	ZCR_EL3	ZCR_EL3
11	110	0001	0010	110	RW	SMCR_EL3	SMCR_EL3
11	110	0001	0011	001	RW	MDCR_EL3	MDCR_EL3
11	110	0010	0000	000	RW	TTBR0_EL3	TTBR0_EL3
11	110	0010	0000	010	RW	TCR_EL3	TCR_EL3
11	110	0010	0001	100	RW	GPTBR_EL3	GPTBR_EL3
11	110	0010	0001	110	RW	GPCCR_EL3	GPCCR_EL3
11	110	0010	0101	000	RW	GCSCR_EL3	GCSCR_EL3
11	110	0010	0101	001	RW	GCSPR_EL3	GCSPR_EL3
11	110	0100	0000	000	RW	SPSR_EL3	SPSR_EL3
11	110	0100	0000	001	RW	ELR_EL3	ELR_EL3
11	110	0100	0001	000	RW	SP_EL2	SP_EL2
11	110	0101	0001	000	RW	AFSR0_EL3	AFSR0_EL3
11	110	0101	0001	001	RW	AFSR1_EL3	AFSR1_EL3
11	110	0101	0010	000	RW	ESR_EL3	ESR_EL3
11	110	0101	0110	000	RW	TFSR_EL3	TFSR_EL3
11	110	0110	0000	000	RW	FAR_EL3	FAR_EL3
11	110	0110	0000	101	RW	MFAR_EL3	MFAR_EL3
11	110	1010	0001	001	RW	MAIR2_EL3	MAIR2_EL3
11	110	1010	0010	000	RW	MAIR_EL3	MAIR_EL3
11	110	1010	0010	011	RW	PIR_EL3	PIR_EL3
11	110	1010	0010	100	RW	POR_EL3	POR_EL3
11	110	1010	0011	000	RW	AMAIR_EL3	AMAIR_EL3
11	110	1010	0011	001	RW	AMAIR2_EL3	AMAIR2_EL3
11	110	1010	0101	000	RW	MPAM3_EL3	MPAM3_EL3
11	110	1010	1010	001	RW	MECID_RL_A_EL3	MECID_RL_A_EL3
11	110	1100	0000	000	RW	VBAR_EL3	VBAR_EL3
11	110	1100	0000	001	RO	RVBAR_EL3	RVBAR_EL3
11	110	1100	0000	010	RW	RMR_EL3	RMR_EL3
11	110	1100	1100	100	RW	ICC_CTLR_EL3	ICC_CTLR_EL3
11	110	1100	1100	101	RW	ICC_SRE_EL3	ICC_SRE_EL3
11	110	1100	1100	111	RW	ICC_IGRPEN1_EL3	ICC_IGRPEN1_EL3
11	110	1101	0000	010	RW	TPIDR_EL3	TPIDR_EL3
11	110	1101	0000	111	RW	SCXTNUM_EL3	SCXTNUM_EL3
11	111	1110	0010	000	-	CNTPS_TVAL_EL1	-
11	111	1110	0010	001	RW	CNTPS_CTL_EL1	CNTPS_CTL_EL1
11	111	1110	0010	010	RW	CNTPS_CVAL_EL1	CNTPS_CVAL_EL1
"""

with open('arch/aarch64/registers_advsimd_tab.go', 'w') as fp:
    print('// Code generated by "mkreg_aarch64.py", DO NOT EDIT.', file = fp)
    print(file = fp)
    print('package aarch64', file = fp)

    for pfx, ty, sfx, iota in REG_TAB:
        print(file = fp)
        print('const (', file = fp)
        print('    %s0 %sRegister%s = %s' % (pfx, ty, sfx, iota), file = fp)

        for i in range(1, 32):
            print('    %s%d' % (pfx, i), file = fp)
        else:
            print(')', file = fp)

def eval_bits(bv: str, m: int) -> str:
    end = -1
    ret = ''
    pos = bv.find('m[')

    while pos != -1:
        ret += bv[end + 1:pos]
        end = bv.find(']', pos + 2)

        if end == -1:
            raise RuntimeError('invalid bit value')

        val = bv[pos + 2:end].split(':')
        pos = bv.find('m[', end + 1)
        bhi, blo = int(val[0]), int(val[0])

        if len(val) != 1:
            if len(val) != 2:
                raise RuntimeError('invalid bit value')
            else:
                blo = int(val[1])

        for p in range(bhi, blo - 1, -1):
            if m & (1 << p):
                ret += '1'
            else:
                ret += '0'

    ret += bv[end + 1:]
    return ret.replace(':', '')

KEY_ORDER = [
    'CRm',
    'CRn',
    'o0',
    'op1',
    'op2',
]

ACCESS_BIT_TAB = {
    '-'  : '11',
    'RO' : '10',
    'WO' : '01',
    'RW' : '11',
}

sysregidx = 0
sysregtab = {}
sysreghdr = []
sysregenc = set()

for line in filter(None, map(str.strip, SYS_REG_TAB.splitlines())):
    data = line.split()
    assert not sysreghdr or len(data) == len(sysreghdr)

    if not sysreghdr:
        sysreghdr = data
        continue

    reg = dict(zip(sysreghdr, data))
    reg['idx'] = sysregidx

    mnemonic = reg['Mnemonic']
    sysregidx += 1

    if len(reg['op0']) != 2 or reg['op0'][0] != '1':
        raise RuntimeError('invalid op0')

    reg['o0'] = reg['op0'][1:]
    reg['rw'] = ACCESS_BIT_TAB[reg['Access']]

    if '<m>' not in mnemonic:
        if mnemonic not in sysregtab:
            sysregtab[mnemonic] = reg
            continue

        if any(reg[k] != sysregtab[mnemonic][k] for k in KEY_ORDER):
            raise RuntimeError('system register encoding confliction')

        acc0 = reg['rw']
        acc1 = sysregtab[mnemonic]['rw']
        sysregtab[mnemonic]['rw'] = ''.join(str(int(a) | int(b)) for a, b in zip(acc0, acc1))
        continue

    maxbit = -1
    minbit = 99999

    for cell in data:
        if 'm[' in cell:
            pos = cell.index('m[')
            bvs = list(map(int, (cell[pos + 2:cell.index(']', pos)].split(':'))))
            maxbit, minbit = max(maxbit, *bvs), min(minbit, *bvs)

    if minbit != 0:
        raise RuntimeError('invalid lowest bit')

    for bv in range(1 << (maxbit + 1)):
        sreg = dict(**reg)
        name = mnemonic.replace('<m>', str(bv))

        for fn in ['CRm', 'CRn', 'o0', 'op1', 'op2']:
            sreg[fn] = eval_bits(sreg[fn], bv)

        sreg['idx'] = sysregidx
        sreg['Mnemonic'] = name
        sysregidx += 1

        if name not in sysregtab:
            sysregtab[name] = sreg
            continue

        if any(sreg[k] != sysregtab[name][k] for k in KEY_ORDER):
            raise RuntimeError('system register encoding confliction')

        acc0 = sreg['rw']
        acc1 = sysregtab[name]['rw']
        sysregtab[name]['rw'] = ''.join(str(int(a) | int(b)) for a, b in zip(acc0, acc1))
        continue

with open('arch/aarch64/registers_sys_tab.go', 'w') as fp:
    print('// Code generated by "mkreg_aarch64.py", DO NOT EDIT.', file = fp)
    print(file = fp)
    print('package aarch64', file = fp)
    print(file = fp)

    rtab = list(sysregtab.values())
    rtab.sort(key = lambda x: x['idx'])

    row0 = next(iter(rtab))
    rwoffs = sum(len(row0[fn]) for fn in ['CRm', 'CRn', 'o0', 'op1', 'op2'])

    print('const (', file = fp)
    print('    _SR_rwoffs  = %d' % rwoffs, file = fp)
    print('    _SR_regmask = %#x' % ((1 << rwoffs) - 1), file = fp)
    print(')', file = fp)
    print(file = fp)
    print('const (', file = fp)

    for reg in rtab:
        print('    %(Mnemonic)-18s SystemRegister = 0b%(rw)s_%(CRm)s_%(CRn)s_%(o0)s_%(op1)s_%(op2)s' % reg, file = fp)
    else:
        print(')', file = fp)

    print(file = fp)
    print('var _SysRegisters = map[string]SystemRegister {', file = fp)

    for reg in rtab:
        name = reg['Mnemonic']
        print('    %-20s : %s,' % ('"%s"' % name, name), file = fp)

    print('}', file = fp)
    print(file = fp)
    print('var _SysRegisterNames = map[SystemRegister]string {', file = fp)

    for reg in rtab:
        out = '    %(Mnemonic)-18s : "%(Mnemonic)s",' % reg
        enc = '%(rw)s_%(CRm)s_%(CRn)s_%(o0)s_%(op1)s_%(op2)s' % reg

        if enc in sysregenc:
            continue

        print(out, file = fp)
        sysregenc.add(enc)

    else:
        print('}', file = fp)
